The “High” signal between words
I can observe that here too, and found not a way to change that behavior. Looking at the timing diagram in the Vybrid Reference Manual (Chapter 12.4.4.4.1 Classic SPI Transfer Format) shows that the behavior is expected. I hooked up an oscilloscope, and it shows that the transition is well after the rising edge. Given that we sample on rising edge (CPOL=0, CPHA=0), this behavior should really not be a problem (see also this timing diagram, the MOSI signal level is undefined in this phase).
[upload|OcXtRyo4ub05aBF+BPnjMZenx2k=]
[upload|tI34sTmha6RMcO5naZbdi8keXx4=]
Peak in the Chip-Select signal
I tried to reproduce that behavior here, without success. My test setup consisted of a user space application continuously sending 3 x 0x8000 in a Linux SPI transfer using /dev/spidev1.0. Using SPI_IOC_WR_BITS_PER_WORD to request 16 bits, and SPI_IOC_WR_MAX_SPEED_HZ requesting 10MHz. I also added the delays in the device tree. To capture a peak, I used a PWM trigger on the CS signal, triggering to any signal which is low for shorter than 3.5us (which is well below one transfer length). I let that run for about 5 minutes, so thousands of transfers must have passed, the Oscilloscope never caught anything.
[upload|tEhMa+MEz9x0/1HqxsQb8FosfiI=]
It seems to me that your Logic Analyzer is really capturing something erratic, maybe a reflection or something similar. What you can try is using less drive strength and configure the pad to 50MHz:
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD5__DSPI1_CS0 0x02e2
VF610_PAD_PTD6__DSPI1_SIN 0x02e1
VF610_PAD_PTD7__DSPI1_SOUT 0x02e2
VF610_PAD_PTD8__DSPI1_SCK 0x02e2
>;
};