Not getting proper clock for the SPI2 in apalis T30


In my project i need to use SPI2 signals(From the apalis T30 data sheet its clear that apalis SPI2 signals are mapped to T30 SPI controller 5).

So i tried to map the T30 SPI controller 5 to make the use of SPI2. I have made the below required changes.

  1. in the drivers/spi/spi-tegra.c

used “SLINK 2B-5 7000:dc00” to get the resource for the T30 controller 5. So in the probe i have used

base_ptr = ioremap_nocache(0x7000dc00 , 3072); //to get the base pointer for the controller 5.

then tried to set the required clock of 15Mhz(In the same way as i have done for the SPI1 and it is working fine) through

set_best_clk_source(tspi, 15000000);

Then in the spi-tegra driver made the changes to select the SPI2_CS2.

  1. In the device file (arch/arm/mach-tegra/devices.c) made the changes to get the resource for the tegra SPI5 device

kept the default name(spi_tegra) for the struct platform_device tegra_spi_device5 and for the other devices changed to different name to avoid the multiple instances of probe function.

eg: for spi device 5 i have kept the same name:

struct platform_device tegra_spi_device5 = {

    .name           = "spi_tegra",

but other devices, changed the names alone to avoide multiple instances.

struct platform_device tegra_spi_device1 = {

    .name           = "spi_tegra_0",

    .id             = 0,

After the changes once i am installing the spi-tegra.ko through insmod, i am not getting the required 15Mhz clock. Near 3Mhz clock is coming.

I also tried to change the clock from 15Mhz to other values but there is no effect.

In the device.c i tried to comment the “CONFIG_ARCH_TEGRA_2x_SOC” for the tegra spi device 5 and 6 but there is no effect.

I have also disabled LCD_SDOUT, LCD_SDIN, LCD_CS0_N and LCD_SCK from the “arch/arm/mach-tegra/board-apalis_t30-pinmux.c” to avoid the conflict but there is no effect.

I can see the SPI controller is registered.


root@apalis-t30:~# ls -l /sys/class/spi_master/spi4/

lrwxrwxrwx 1 root root 0 Jan 15 19:13 device → …/…/…/spi_tegra.4

drwxr-xr-x 2 root root 0 Jan 15 19:13 power

lrwxrwxrwx 1 root root 0 Jan 15 19:13 subsystem → …/…/…/…/…/class/spi_master

-rw-r–r-- 1 root root 4096 Jan 15 19:11 uevent


root@apalis-t30:~# ls -l /sys/class/spidev/


So can you please help me to get the required clock?

Is there any particular reason for you to set this question on private? With private questions, there is no way for the community to provide feedback or profit from any feedback.

I don’t really understand what exactly you are trying to achieve. Why exactly can’t you just use our regular Apalis SPI2 configuration?

Hi Marcel,

There is no specific reason to set the private. I was thinking if modifying the core things that should not go to outside because of some security reasons.

Hi Marcel,

I have already explain, why i was modifying the core driver(Because i was unable to meet our requirement while using the default spi-tegra driver).
To meet our requirements i am trying to modifying the spi-tegra driver. And in this way i am able to achieve our requirements.

Sure, then please just look at our regular configuration in which case obviously clocking works properly. Thank you!

Hi Marcel,

I have checked that and in the same way i have modified for the SPI 1 and it works fine, but for SPI2 it is not working.

For SPI 1 mapping is same for T30 SPI controller 1 but SPI2 is mapping with T30 SPI controller 5.

Thats what i am not getting where problem is.

Hi Marcel,

i am not getting the required clock to SPI2 while changing the clock through set_best_clk_source(tspi, 15000000);

Because in this way set_best_clk_source() is not able to change the required clock because of the parent clock.

Once tried to print the “struct spi_tegra_data” elements and compared with SPI1 (T30 SPI controller 1) then observed that for the SPI 2 ((T30 SPI controller 5) not getting the parent clock and min_div and parent_clk_count getting 0.

from the print logs:



but in case of SPI1 min_div = 5 and parent_clk_count=2 and is setting parent clock pll_p.

from the print logs:



spi_tegra spi_tegra.0: Setting clk_src pll_p

So tried to understand how SPI1 is getting parent clock.

In board file(arch/arm/mach-tegra/board-apalis_t30.c)

we have a parent clock structure and assigning parent clock(pll_p) for the SPI1 (T30 SPI controller 1)

static struct spi_clk_parent spi_parent_clk[] = {

    [0] = {.name = "pll_p"},

So in the same way i tired to assign the parent clock for the SPI2(T30 SPI controller 5).

static struct spi_clk_parent spi_parent_clk[] = {

[0] = {.name = "pll_p"},

[4] = {.name = "pll_p"}, //kernel it self not booting

After assigning the parent clock kernel it self not booting and getting hung after the below boot up message:


Loading Kernel Image … OK

Starting kernel …

So how to assign parent clock the SPI2?

As already explained, please check our regular configuration. If you need help in modifying the spi driver, then contact one our Partners.

Thank and best regards, Jaski