Memory access atomicity with 16 bit access to DDR3L memory

I have a doubt: i.MX 6ULL is a 32 bit processor ?
Inside description of Colibri product I see: “NXP® i.MX 6ULL, 1x Arm Cortex™-A7, 800 MHz, 1GB DDR3L (16 Bit), 4GB eMMC”. So the access to RAM memory (I presume it is the DDR3L) that is 16bit long, is made with 2 access to it ?
Could you explain me more about atomicity of a write or read to DDR3L memory ?
What I’m expected is that when the processor write a 32 bit lengh data, also if it is made in 2 step, the atomicity is guaranted.


There’s a (128? bit) cache on top of your RAM! 16 or 32 bit DDR RAM - is about memory bandwidth and performance, not about atomicy. You have not only L1/L2 cache sitting on top of RAM, you have as well DDR controller, which usually has something like “Page hit/page miss optimizations”, which is kind of yet another cache…

If you fear about atomicy, you should understand the mechanism it could bite you. Question is about someone/something else (another core, DMA controller, interrupt handler, etc), which could affect your (thread?) read/write result doing its own ±simultaneous write. DDR RAM clearly isn’t that something.

My fear for example is about writing the same 32bit variabile form 2 different process or thread.

You threads/processes just need to write it in single 32bit access. It even doesn’t need to be aligned to 32bits boundary.

Hello @Massimo ,

Were you able to solve your issue with the info provided by @Edward ?

Best regards,

Hello @josep.tx,
I consider closed this topic.
I will test the suggestions received.