Hi,
I’m developing a custom Ethernet driver under Linux (Linux colibri-imx7-emmc 4.9.166-2.8.6+gd899927728be) for Colibri iMX7D 1GB on Aster carrier board. It’s a user mode driver, it uses a self-made mapping kernel mode diver for direct IO access. My Ethernet driver communicates with MAC and PHY directly, for this, the linux fec driver has to be either unbinded or not loaded at all.
The problem is, as long as the standard fec driver is unloaded there is no MDIO connection to PHY (KSZ8041), which is connected according to Colibri iMX7D manual over RMII. Right now I can access and configure ENET1, but cannot access PHY over MDIO.
I understand, if i unbind/unload the standard fec driver, i have to take care of proper initialization and configuration of ENET1 and PHY; moreover i have to configure and gate clocks and pins as well. But it seems, I’m still missing something.
I’ve studied iMX7D Reference Manual, linux DTS files and drivers sources and also examined registers values with and without standard driver loaded. Now I have the following initialization sequence (in pseudo-code):
Configure and gate clocks:
CCM_ANALOG_PLL_ENET := 0x80000300 // activate ENET PLL
CCM_CCGR112 := 0x00000003 // gate clock for ENET1
CCM_CCGR6 := 0x00000003 // gate clock for ENET1
ENET_AXI_CLK_ROOT := 0x17000001 // select and activate SYS_PLL_PFD4
ENET1_REF_CLK_ROOT := 0x12000000 // select and activate ENET_PLL_DIV20
ENET1_TIME_CLK_ROOT := 0x11000000 // select and activate ENET_PLL_DIV10
Configure and gate pins:
SW_MUX_CTL_PAD_GPIO1_IO10 := 2 // mode ALT2, MDIO ENET1
SW_MUX_CTL_PAD_GPIO1_IO11 := 2 // mode ALT2, MDC ENET1
IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA := 6 // mode ALT6, MDC ENET1
IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA := 6 // mode ALT6, MDIO ENET1
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 := 2 // mode ALT2, ENET1_REF_CLK ENET1
IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B := 1 // mode ALT1, MDIO ENET1
IOMUXC_SW_MUX_CTL_PAD_SD2_WP := 1 // mode ALT1, MDC ENET1
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0 := 0 // mode ALT0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1 := 0 // mode ALT0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL := 0 // mode ALT0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC := 1 // mode ALT1
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0 := 0 // mode ALT0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1 := 0 // mode ALT0
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL := 0 // mode ALT0
// pins
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 := 73
IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B := 3
IOMUXC_SW_PAD_CTL_PAD_SD2_WP := 3
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0 := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1 := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0 := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD := 73
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL := 73
In other words I’m trying to manually mimic initialization and configuration steps done by linux driver.
I’ve already played a lot with different clocks, gates and pins configurations and parameters and still cannot access PHY.
What am I doing wrong?
Is there some kind of a step-by-step manual or list of things needed in order to configure ENET1 and PHY properly?
Best regards