The cause is likely related to the selection of LDB parent clock. This is done in arch/arm/mach-imx/clk-imx6q.c. There are several relevant commits made to the 3.14.52 kernel which are not present in 3.14.28. You may need to manually change the parent clock. This can be done with the following patch to the 3.14.28 kernel:
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 8669c92..e62824c 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -511,6 +511,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
}
+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
With this commit, you can now set the parent clock in the 3.14.52 device tree.
Any specific reason for not having this patch integrated in toradex kernel branch?
What is triggering the problem? Pixel clock value or LVDS is just not working in this kernel?