LT8912B DSI-to-HDMI bridge: MIPI RX never locks input (sync counters stay 0) on Verdin iMX95 / Torizon — DSI host VPG also fails, upstream proven innocent

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Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

I understand you’re experiencing MIPI DSI synchronization issues with the LT8912B bridge on your Verdin iMX95. Based on the community discussions and documentation, here are some insights that may help:

Clock Configuration and Continuous Clock Mode

For MIPI DSI clock configuration on Toradex modules, the clock settings are typically managed through device tree properties(1). The continuous clock requirement you mentioned is a common issue with DSI bridges. While the sources don’t specifically mention the iMX95 DSI controller’s continuous clock configuration, similar issues have been reported on other Verdin modules(2).

DSI Mode Configuration

The community discussions show that DSI mode configuration can be critical for proper bridge operation(2). Your current mode flags (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_NO_EOT_PACKET) appear standard, but the panic when adding MIPI_DSI_MODE_VIDEO_BURST suggests timing incompatibility.

Debugging DSI PHY Activity

For debugging DSI PHY activity without high-bandwidth probes, the community has used kernel tracing methods(3). You can enable function tracing to monitor DSI driver calls:

echo function > /sys/kernel/tracing/current_tracer
echo "*dsi*" > /sys/kernel/tracing/set_ftrace_filter
echo 1 > /sys/kernel/tracing/tracing_on

(3)

Clock Verification

To verify clock status, you can examine the clock summary as you’ve done, and also check(4):

cat /sys/kernel/debug/clk/clk_summary

(4)

Recommendations

Given your thorough testing and the VPG test failure, this appears to be a low-level DSI PHY configuration issue. The fact that your sync counters remain at zero strongly suggests either:

  1. Clock continuity issue - The DSI PHY may not be providing continuous clock
  2. Lane mapping or differential signaling issue - Despite clean schematic mapping
  3. DSI timing parameters - The bridge may require specific timing that differs from default

Next Steps

I’d recommend checking if there are any Verdin iMX95-specific device tree properties for DSI clock configuration. You might also want to examine the exact DSI timing parameters being sent to ensure they match the LT8912B’s requirements.

The community discussions suggest that MIPI DSI issues often require platform-specific configuration adjustments(2)(4).

Best regards, Toradex AI Assistant.

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