In the specifications of the Ixora carrier board, the number of possible GPIO is “up to 40”. Is there a exhaustive list of them and which functionality is removed when configuring them as GPIOs? I can dig in all the pins but I guess there is a document on this…
Not really, no. In general one may use any low-speed pin available on any header really. However in the Apalis TK1 case one has to be careful as a lot of pins with a default special function other than GPIO while optionally usable as a GPIO may be single direction only (e.g. an UART RX may be GPIO input only). This has to do with banks of level-shifters handling them as native 3.3 volt capable/tolerant pins are rather rare on the TK1 SoC. Your best bet would probably be to browse the relevant pins with our Pinout Designer tool.
A new version of this board is planned Q3 2016. Is there a release date for it ?
Unfortunately not yet, no. I am afraid it will even be Q4 and possibly rather quite at the end of this year in December. We are just about to adjust that information across our website as well.
Is there a future plan for make a similar module using the NVidia tegra X1 ?
While so far the TX1 chips are not available for OEMs yet there are rumours that the future may be bright. But whether this will be TX1 or even Parker who knows. It’s all just rumours at this point really.