I currently have the Apalis TK1 connected to my FPGA via PCIe (x1). I see that the Apalis should support x2. Is this actually supported and is there any issues, assuming the I/O is available?
Would this limit future compatibility?
I currently have the Apalis TK1 connected to my FPGA via PCIe (x1). I see that the Apalis should support x2.
Yes, if by Apalis you mean the Apalis TK1.
Is this actually supported and is there any issues, assuming the I/O is available?
While so far we did not have any carrier board where we would be able to test this it should in general work and we will support any customer designing a custom carrier board making use of this.
Would this limit future compatibility?
That depends. The Apalis standard only requires one single PCIe lane. As for type specific interfaces/pinmux’ we try to make future modules compatible however while e.g. Apalis T30 had a separate quad lane PCIe port available Apalis TK1 only has an additional lane meant to go with the regular Apalis PCIe port. The upcoming Apalis iMX8 might support both an additional PCIe port as well as lane but how exactly is still being discussed.