Invert logic of RTS port - apalis-uart2(ttyLP3)

Hi,
How can I invert RTS pin logic on apalis-uart2?
I connected pins of RS485 transceiver DE, DI to apalis UART3_RTS_B.
For transmission I need a high logic level on this output but it is low, I try to use “rs485-rts-active-low” but it didn’t change anything.
“rs485-rts-active-low” works perfectly for apalis-uart1.

My module: Apalis IMX8QP 2GB

without “rs485-rts-active-low”:

/* Apalis UART2 */
&lpuart3 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_lpuart3>;
linux,rs485-enabled-at-boot-time;
};

with “rs485-rts-active-low”:

/* Apalis UART2 */
&lpuart3 {
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_lpuart3>;
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
};

pinctrl_lpuart3:

/* Apalis UART2 */
pinctrl_lpuart3: lpuart3grp {
fsl,pins =
<IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020>,
<IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020>,
<IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020>,
<IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020>;
};

Hello,

can you share a quick snippet of you schematic and how you connected it on you carrier board?

Best Regards,

Matthias Gohlke

Hello @rzor112,

do you still need help here? You did not yet share a schematic with us that we can check.

Best Regards,

Matthias