Hello @vix,
As you already figured out, NVIC provides the interrupt controller that is tightly coupled to
Cortex-M based processor cores. You need to ensure that your M7 firmware is correctly handling the interrupts. The firmware should be configured to use the NVIC (Nested Vectored Interrupt Controller) for interrupt handling on the M7 core.
So to begin with, as you found out from NXP forum, you need to decide which GPIO bank(s) should be assigned to Cortex-M. Currently, Torizon is using GPIO banks starting from 1 to 5 for different interfaces on the verdin i.MX8MP SOM. You can look through the device tree files for the SOM to understand what interfaces are using which GPIO banks and you need to disable the GPIOs that you don’t need. You can do that in the HMP overlay file.
After that you need to modify your M7 firmware files as follows (this is an example where we had to use an encoder):
uint8_t tdxenc_new_enc(
GPIO_Type *gpio_a_base,
const uint32_t gpio_a_pin,
const IRQn_Type gpio_a_irqn,
GPIO_Type *gpio_b_base,
const uint32_t gpio_b_pin,
const IRQn_Type gpio_b_irqn,
const bool reverse
) {
const gpio_pin_config_t gpio_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0,
.interruptMode = kGPIO_IntRisingOrFallingEdge,
};
// Init GPIOs as input with rising edge and falling edge interrupts
GPIO_PinInit(gpio_a_base, gpio_a_pin, &gpio_config);
GPIO_PinInit(gpio_b_base, gpio_b_pin, &gpio_config);
EnableIRQ(gpio_a_irqn);
GPIO_PortEnableInterrupts(gpio_a_base, 1 << gpio_a_pin);
EnableIRQ(gpio_b_irqn);
GPIO_PortEnableInterrupts(gpio_b_base, 1 << gpio_b_pin);
// rest of the code
return enc_index;
}
void GPIO1_INT0_IRQHandler() {
// Handler Code
SDK_ISR_EXIT_BARRIER;
}
encoder_1 = tdxenc_new_enc(
GPIO1, 0, GPIO1_INT0_IRQn,
GPIO1, 1, GPIO1_INT1_IRQn,
!reversed
);
In the above code, I assumed that you disabled GPIO1 and are using pin 0. You will need to write your own handler and will have to tweak the code as per your needs. Let us know if this helps.