as you mentioned the PHY generates an interrupt on pin GPIO1_IO10. who is managing the interrupt? the fec driver? where I can find the source code of the interrupt handler?
I assumed the interrupts was purely for the sake of the PHY driver: micrel.c « phy « net « drivers - linux-toradex.git - Linux kernel for Apalis, Colibri and Verdin modules
Though on closer inspection I can see that in the device tree the pinctrl group for fec1 uses GPIO1_IO10 as well: imx8mm-verdin.dtsi « freescale « dts « boot « arm64 « arch - linux-toradex.git - Linux kernel for Apalis, Colibri and Verdin modules
I would assume then that fec1 has knowledge/visibility of this pin as well. How it makes use of this shared pin software-wise, is not clear to me. Perhaps so it’s just fec and phy have the same interrupt source in order to have synchronized interrupts.
As for the actual interrupt handler I think it’s just here in the generic phy.c source code: phy.c « phy « net « drivers - linux-toradex.git - Linux kernel for Apalis, Colibri and Verdin modules
I can see that the wol register is explicitly masked for MAGIC_PACKETS, I wonder if the same happens on the interrupt handler, responding only to magic_packet events and ignoring all the others
This could be a possibility. NXP typically prevents/blocks behavior that is not supported by them.
Best Regards,
Jeremias