IMX8 spi multi chip select

I want to use SPI0 and SPI2, each spi connects 2 slave devices.
I found each spi has cs0 and cs1, then I do not need to use GPIO as cs.

&lpspi0 {

num-cs = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi0>;
#address-cells = <1>;
#size-cells = <0>;
dma-names = "no","no";

spidev00: spi@0 {
	compatible = "toradex,evalspi";
	reg = <0>;
	spi-max-frequency = <4000000>;
spidev01: spi@1 {
	compatible = "toradex,evalspi";
	reg = <1>;
	spi-max-frequency = <4000000>;


I use this device tree, but I can not get /dev/spidev0.1, there is only spidev0.0

dmesg | grep spi

[ 0.801484] fsl_lpspi 5a000000.lpspi: cs1 >= max 1

[ 0.806342] spi_master spi0: spi_device register error /lpspi@5a000000/spi@1

[ 0.813404] spi_master spi0: Failed to create SPI device for /lpspi@5a000000/spi@1

[ 0.813529] fsl_lpspi 5a000000.lpspi: dma setup error -19, use pio

It seems that there is only one cs, we can not use cs1.

I read this question:

then I try to use gpio as cs:

&lpspi0 {

num-cs = <2>;
fsl,espi-num-chipselects = <2>;
cs-gpios =<&gpio6 19 GPIO_ACTIVE_LOW>,
                <&gpio6 20 GPIO_ACTIVE_LOW>;

it works. I found devices: /dev/spidev0.0, /dev/spidev0.1

so, how can I use spi cs1 pin instead of gpio?

Could you please clarify what exactly you are trying to achieve?

iMX8 SPI hardware block has only only Chip Select signal per channel. So you can communicate only with one device using HW CS signal. On a software level you can use a GPIOs as a chip select so you can communicate with more than one device per channel. SPI driver will assert specific GPIO line configured by Device Tree when communicating with selected sub channel.

I do not know how many chip selects for imx8qm chip, but I found file include/dt-bindings/pinctrl/pads-imx8qm.h in linux source code.

#define SC_P_SPI0_CS0                            120  /* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
#define SC_P_SPI0_CS1                            121  /* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */    
#define SC_P_SPI2_CS0                            125  /* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */    
#define SC_P_SPI2_CS1                            126  /* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */

it seems that each spi has 2 cs.
I can not find reference manual for imx8qm, but I found those for imx8dx/8mm, these pdf files have about 8000 pages. who can tell me where is the reference manual for imx8qm?

Since it not Toradex SOM specific question but rather NXP related i’d recommend to use NXP community -