iMX7D M4 for hard realtime

We are considering to use the iMX7 M4 core for realtime tasks in one of our next products. According to the NXP iMX7D reference guide all peripherals are shared between the A7 and M4 cores via a “AXI and AHB Switch Fabric”. How are priorities managed when both cores are using different resources via the same bus? Lets say the A7 cores needs to constantly access the RAM at a high rate and maybe use the camera interface simultaneously, whereas the M4 core wants to perform SPI communication. Additionally both cores need to communicate via the RPMSG interface. Will there be any impact on the realtime operations?

Hi @qojote !

The peripheral assignment is controlled by the Resource Domain Controller (RDC) inside the SoC. The RDC assures there’ll be no conflicts between the cores such as both trying to use the same peripheral at the same time.
Also, the code loaded to the M4 usually runs in the Tightly Coupled Memory (TCM), which is separate from the Linux domain and yields best performance. You can also use the OCRAM or the DDR, but this will result in slower performance.

All of this should guarantee there’s no impact on the core operations themselves, thus allowing hard real-time behavior within all the existing constraints (e.g. maximum SPI clock).

There is no simple answer to your question. Mainly it depends on your exact requirements. An AXI is fast and transaction based, so in general you SPI operation should be fast enough. The M4 core has 64KB of it’s own memory (TCM) so it’s highly recommended to fit your app in that memory to not be affected by A7 memory access. For deeper inquiry I’d recommend to use NXP community.

Hi @gustavo.tx,
I already figured out how the RDC is working and i was able to configure the resources for each core. I am planning to only use the TCM plus eventually the OCRAM. Let me precise my question. I need utilize the SPI interface and a high precision counter on the M4 side.

Hi @alex.tx,
My concern is not about the SPI transaction speed in general but at least i need to know the worst case scenario delay. Much more important is the usage of a high precision counter. I want to send SPI commands at a well defined intervall. Timing resulution should be ideally in sub-microseconds.

OK you can definitely do this.

I’d recommend to ask NXP about it since it purely SOC related. We don’t have such a numbers.
But again - what are your requirements?

I want to monitor a GPIO pin to start sending SPI commands to different devices within a well-defined time. Once started the SPI commands should be repeated with a specified interval (some microseconds). Therefore a high resolution timer should be used (e.g. downcounting and generating interrupt). Timing is crucial in that application.

Hi @qojote

This can be realized using M4. Regarding the exact delay and time resolution, as @alex.tx already said, you need to try this out or ask NXP.

Best regards,