Hi @Gowthami , @alex.tx , @jaski.tx
Probing NAND chip RE# pin while executing ubi read ${kernel_addr_r} kernel command I saw ~1.4MHz clock. That would be up to 1.4MB/s in the best case. Macronix NAND used in Colibri modules, under Linux shows over 20MB/s read from /dev/mtdN speed. Loading 5MB kernel in U-Boot takes more than 5 seconds.
Please take a look at U-Boot code and
board/toradex/colibri-imx6ull/colibri-imx6ull.c
static void setup_gpmi_nand(void)
{
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
}
Calculated bitmask above in setup_gpmi_io_clk() lands in CCM_CS2CDR register. Relevant bit field offsets in CS2CDR are 21 and 18:
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
Inappropriately used offsets are
#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22
#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19
Without figuring out what should be the best NAND IO clock, just commenting contents of above routine and thus leaving NAND speed the same like it was booting U-Boot, kernel load from flash time improves about 5 times.
Edward
