How to Define RS485 in Device Tree

By default all the free pins are pin-muxed as GPIOs. One need to make sure there are no pin conflicts when using them. I tested it at my end, worked as expected.
Below is the diff:

diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 8392dcd..ad37853 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -168,6 +168,7 @@
 
 &uart1 {
        status = "okay";
+       linux,rs485-enabled-at-boot-time;
 };
 
 &uart2 {
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index d62c4f6..3d8462b 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -189,7 +189,6 @@
                                VF610_PAD_PTA30__GPIO_20        0x22ed
                                VF610_PAD_PTA31__GPIO_21        0x22ed
                                VF610_PAD_PTB6__GPIO_28         0x22ed
-                               VF610_PAD_PTB7__GPIO_29         0x22ed
                                VF610_PAD_PTB12__GPIO_34        0x22ed
                                VF610_PAD_PTB13__GPIO_35        0x22ed
                                VF610_PAD_PTB16__GPIO_38        0x22ed
@@ -200,7 +199,6 @@
                                VF610_PAD_PTC1__GPIO_46         0x22ed
                                VF610_PAD_PTC2__GPIO_47         0x22ed
                                VF610_PAD_PTC3__GPIO_48         0x22ed
-                               VF610_PAD_PTC4__GPIO_49         0x22ed
                                VF610_PAD_PTC5__GPIO_50         0x22ed
                                VF610_PAD_PTC6__GPIO_51         0x22ed
                                VF610_PAD_PTC7__GPIO_52         0x22ed
@@ -364,6 +362,8 @@
                        fsl,pins = <
                                VF610_PAD_PTB4__UART1_TX                0x21a2
                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                               VF610_PAD_PTC4__UART1_RTS               0x21a2
+                               VF610_PAD_PTB7__UART1_CTS               0x21a1
                        >;
                };