I planning to use the M4 core of VF61 to perform real time tasks such as ad conversion, enable/disable devices etc. It was easy to disable ADC’s following the Device Tree Customization article but I can’t find how to disable one or more GPIO pins.
Can anyone help me?
If any specific GPIO is used by any driver, one can remove that GPIO from the respective device tree node. e.g the GPIO used as external interrupt source for external CAN chip over spi on eval board.
The free pins are configured as GPIOs in the device tree by default, those are not enabled until one uses them from userspace via GPIO sysfs intereface. If to completly remove the GPIO io mux configuration from device tree one can remove the GPIO definitions from the device tree.
The GPIO’s are organized in banks. A GPIO bank handles 32 GPIO’s. If you want to have exclusive access from the M4 to a full bank, you would have to make sure that none of the pins are used as a GPIO by the A5, and remove/disable the bank on A5/Linux side (see vfxxx.dtsi, by using a reference to the node you can disable the GPIO bank also in your board level dts).
You can also share the GPIO bank, in that case both cores access the same GPIO bank. You need to make sure that the two cores come along (e.g. if you enable interrupt on a pin which is handled by the M4, make sure that the A5 does not handle the interrupt and visa versa). Since most GPIO operations (set/clear/read) are atomic operations thanks to dedicated clear/set registers, it should be possible to share a GPIO bank without the need of a locking mechanism. That is what we did in the demo applications we created on eCos.
The pin access is related, but somewhat different story. Pinctrl happens in the IOMUXC module, which is also shared between the cores. However, that module has one register per pin, hence you just need to make sure that the pins you configure on the two cores are orthogonal. E.g. you should remove all pinctrl entries from the device tree for the pins you plan to use on the M4. With that Linux on the A5 core won’t touch that pin.