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LVDS Display Configuration for Verdin iMX8M Plus
I can help guide you through the LVDS display integration process for your custom carrier board with the Verdin iMX8M Plus module.
Hardware Considerations
The Verdin iMX8M Plus features native LVDS capability through its i.MX 8M Plus SoC (1). The LVDS interface can be configured for single or dual-channel with 18-bit and 24-bit color depth (2)(1). Key specifications include:
- Single channel: Up to 1366x768 pixels @60fps (80MHz pixel clock maximum) (2)(1)
- Dual channel: Up to 1920x1080 @60fps (160MHz pixel clock maximum) (2)(1)
- Color mappings: JEIDA format (Intel 24.0) and VESA format (Intel 24.1) (2)(1)
Important Note: The LVDS signals are on module-specific pins and are not guaranteed to be compatible with other Verdin modules (2)(1). For compatibility with other Verdin modules, consider using a MIPI DSI to LVDS bridge IC on the carrier board (1).
Software Configuration Approach
Based on successful community implementations (3)(4), you’ll need to create a custom device tree overlay that defines your display’s timing parameters. The key steps include:
- Create Device Tree Overlay: Define a
panel-lvdsnode with your display’s specific timing parameters (3) - Configure Display Timings: Set parameters like
hactive,vactive,hsync-len,vsync-len,hfront-porch,vfront-porch,hback-porch, andvback-porchaccording to your LCD datasheet (3) - Set Data Mapping: Configure
fsl,data-mappingandfsl,data-widthproperties to match your panel’s color format (3)
Hardware Verification Process
Rather than submitting your LCD datasheet directly, I recommend following this systematic approach:
- Review LVDS Pin Mapping: Verify your carrier board connections match the LVDS interface signals documented in the Verdin iMX8M Plus V1.1 datasheet, Table 18 (1)
- Check Power Requirements: Ensure proper power supply for your display panel
- Validate Timing Parameters: Extract the exact timing specifications from your LCD datasheet
- Test with Reference Configuration: Start with a known working overlay and modify the timing parameters
Next Steps
To assist you effectively, please share:
- Your LCD panel’s timing specifications (resolution, refresh rate, sync timings)
- Current device tree overlay configuration
- Any error messages from the kernel logs
- Details about your carrier board’s LVDS signal routing
This information will help provide more targeted guidance for your specific display integration.
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