Dear @maha
I implemented the code on my system to verify the functionality. Attached to this comment you find a source code which worked for me:
A write and a read on each chip select looks as follows:
CH1: CS0 (SODIMM 105)
CH2: CS1 (SODIMM 107)
I assume the major error in your code was the value of IOMUXC_GPR_GPR1. The low 12 bits of this register must be configured to 0x01b (instead of 0x02d). I adjusted my previous answer accordingly.
Regards, Andy