I want to implement a dual-core lockstep on the colibri IMX7D 1GB.
I want to implement the dual-core lockstep (DCLS) with two A7 CPU’s, one M4 CPU and the RAM or an external memory (if the RAM offers not enough memory space). The objective of this project is to understand how a dual-core lockstep is implemented (if it works slow it’s not a problem, but it has to work).
The DCLS is a safety system on embedded systems. We have two CPU’s which are working in parallel and they’re executing exactly the same set of operations at the same time. In this set of operations we have verification points. If a verification point is achieved, the two CPU’s are stopped and the Checker module compares the outputs of the CPU’s and also their context(General purpose registers and others), which are saved in the RAM or an external memory at different addresses. When these outputs and contextes are the same we can execute the outputs of this CPU’s, if not then we have to repeat the set of operations.
So I thought that the colibri IMX7 satisfy my needs. CPU 1 and 2 are the A7 cores and the checker module is the M4 core. But I have problems with the memory.
I don’t understand how the memory for the A7 cores are managed and how I could change this, if it’s even possible.
Also I would like to know your opinion about this project. Is a DCLS implementable on the colibri IMX7D 1GB?