Display settings on i.MX6ULL

I am trying to set up a display on imx6ull and our customer carrier board.
We have a 4.3" WQVGA (480x272) display with resistive touch screen.
Following this article and this forum thread, I changed the u-boot setting as below:

Colibri iMX6ULL # setenv vidargs video='mxsfb:480x272M-16@60'
Colibri iMX6ULL # saveenv

However, after kernel bootup, the LXDE GUI is not centered on the display. See the attached picture.What am I missing here?


Most likely timing calculation fails which the full textual boot log may reveal. Try using R instead of M or further suggestions as per modedb documentation: http://git.toradex.com/cgit/linux-toradex.git/tree/Documentation/fb/modedb.txt?h=toradex_4.14-2.3.x-imx

Also what exact hardware (module and carrier board) and software versions of things are you talking about?

The exact make and model of the display may also be if interest.

I tried using R instead of M and the screen became all white. Also tried other arguments. The only argument that makes it work better is “i” for interlaced mode (480x272M-16@60i), where the GUI moved a little bit (about half way) toward display center. Not sure what argument we should use.

We are using this TIANMA display
The linux image version is Colibri-iMX6ULL_LXDE-Image 2.8b6.184 20190401

Here is the dmesg log for original vidargs setup (video=‘mxsfb:480x272M-16@60’)

hi @wjzhang

Could you share the output of fbset and the connection diagram of your display to the carrier board?

Have you done any changes to the devicetree or any other files? If yes, could you share the changes.

Best regards,

Below is the output of “fbset”:

mode "480x272-58"
    # D: 11.250 MHz, H: 16.741 kHz, V: 57.530 Hz
    geometry 480 272 480 272 16
    timings 88888 96 48 6 3 48 10
    vsync high
    rgba 5/11,6/5,5/0,0/0

This This is the schematic of display interface of our customer carrier board.

No, we have not changed anything in either the kernel image or device tree.

By the way, the same display works with Colibri iMX6 256MB IT V1.1A flawlessly on same carrier board (vidargs is set as ‘video=mxcfb0:dev=lcd,EDT-480x272,if=RGB666’ in u-boot).

hi @wjzhang

Thanks for the schematic. The connections seem to be correct.
Did you try to change the pixclockpol to 1 or 0 and check if this solves your issue?

Best regards,