Data Bus Interface with Spartan6

Good morning,
I made a board with the following interface signals between the iMX6DL toradex and the Spartan 6 FPGA.
NCS0(105), NWE(89), NOE(91), CLK_OUTPUT(168)
ADR_0(111),…., ADR_13(120)
DATA_0(149),…,DATA_15(179)
It is an asynchronous data bus with access to only 16 bus bits and with only 14 address lines.

I would have the following questions:

  1. How can I add one or more wait states during the write phase ?

  2. How can I add one or more waiting states during the reading phase ?

  3. Since the RAM inside the FPGA works only synchronously (it needs a clock signal), if I can give it a “synchronous clock” with the “asynchronous bus”, I can interface in a simpler way.
    On pin 168 if activated as CCM_CLKO1 a frequency of 24mhz comes out. Can I output a “synchronized frequency” with the “asynchronous data bus” ? If yes, how ?
    Maybe selecting on CCM_CLKO1 the same clock frequency with which the micro manages the device “asynchronous data bus”? It’s possible ?

Best Regards

Hi

  1. How can I add one or more wait states during the write phase ?
  2. How can I add one or more waiting states during the reading phase ?
  3. Since the RAM inside the FPGA works only synchronously

The EIM timing is configured from 6 registers. The register values can be set from the device tree with the fsl,weim-cs-timing property described here. The register description can be found in NXP’s i.MX6 reference manual, Chapter 22 External Interface Module (EIM).

Please also refer to the reference manual for the available operating modes and what NXP defines as a synchronous access.

Max

Hi Max,
thank you. I will use device tree for set the timing.
Regards Davide