I made a board with the following interface signals between the iMX6DL toradex and the Spartan 6 FPGA.
NCS0(105), NWE(89), NOE(91), CLK_OUTPUT(168)
It is an asynchronous data bus with access to only 16 bus bits and with only 14 address lines.
I would have the following questions:
How can I add one or more wait states during the write phase ?
How can I add one or more waiting states during the reading phase ?
Since the RAM inside the FPGA works only synchronously (it needs a clock signal), if I can give it a “synchronous clock” with the “asynchronous bus”, I can interface in a simpler way.
On pin 168 if activated as CCM_CLKO1 a frequency of 24mhz comes out. Can I output a “synchronized frequency” with the “asynchronous data bus” ? If yes, how ?
Maybe selecting on CCM_CLKO1 the same clock frequency with which the micro manages the device “asynchronous data bus”? It’s possible ?