Dear @mscaff
Even though I didn’t personally play with the cache so far, I might have some hints for you:
The i.MX7 Reference Manual states in section 4.2.9.3.5:
To use cache, user needs to configure MPU to set those memories as cacheable and all the other memories set as non-cacheable.
It looks like the FreeRTOS implementation provides code for this in the SystemInit() function, which is located at \platform\devices\MCIMX7D\startup\system_MCIMX7D_M4.c. I attached this file for reference.
It would be great if you could post your results here.
Abot the operating frequency:
The examples were provided by NXP, and all implementations I saw so far were using the CM4 at 240MHz. Therefore I strongly assume that the datasheet is not fully correct, and it is safe to operate the M4 at 240MHz.
Regards, Andy