Control pad registering

I am using imx6 quad from scratch for my self learning.

I have a doubt in control pad registering.

As I have look in to the pdf which you providing in your website in the Table 4-3 Pad Control Register

Please help me to find the solution for that

My question is how to review the register and know the description of 9 field.

Thanks in advance if you provided the information will be helpful.

The table 4-3 clearly states that the bit field 8 to 10 are reserved implying they are not used or not to be used.


Please have a look in the kernel documentation on how pinctrl is specified, e.g. here and here.
Additionally the our device tree customization page here.

That tells you that CONFIG value is a 32 bit number, bits 31 and 30 have a special meaning, bits 29 to 0 are written to the Pad Control Register of that pin.

So 0x1b0b1 would translate to the following:

bit 31 not set: do change configuration
bit 30 not set: SION bit in MUX register is set to 0
the rest has the following bit representation:
1 10 1 1 0 000 10 110 00 1
                         - SRE: fast slew rate
                  --- DSE: 25 Ohm @ 3.3V
               --  SPEED: medium
         - ODE: disabled
       - PKE: enabled
     - PUE: pull enabled
  -- PUS: 100 kOhm pullup
- HYS: enabled


 pinctrl_uart4: uart4grp { 
         fsl,pins = < 
                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA     0x1b0b1 
                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA     0x1b0b1 

In the example the PAD name of PAD_KEY_COL0 and signal of UART4_TX_DATA .for this example could please provide the calculation of control pad decoding and how to calculate those HYS,PUE,PUS,ODE,SPEED,DSR,SRE value. as above mentioned in the PAD CONTROL of (0x1b0b1)


Thank you so much for valuable reply.