I am trying to include a MIPI DSI display onto my Colibri iMX8qxp board (a viola, although this post requires none of the viola peripherals) and am having some issues. I suspect it is a problem with a custom interface board I have placed between my SOM and the display. I had a separate engineer do the layout on this interface board, and he used a two layer board without differential routing, length matching, 50-Ohm traces, or any ground planes. I am highly suspicious of this interface board, as the colibri datasheet claims that the maximum skew only allows for a delay caused by 1.5 mm of mismatch. That being said, I want to rule out all other possibilities before moving forward with another board spin. I will outline my bring-up process here (additionally, to help anyone who is starting down this path, as there is quite a lot of information to sort through) and would appreciate pointing out where any errors may lay.
NOTES:
- Display: Riverdi 7.0” TFT MIPI
- uname -r output: 6.6.101-7.4.0-devel
- PCLK Frequency: 51.2 MHz
1.) I followed the existing Toradex Webinar on MIPI development to create my custom driver (uploaded below, everything changed from the defaults is labeled under “Added by C. Castillo”). I then compiled based on a mix of the Toradex instructions as well as embear instructions. I pushed to my device and can successfully modprobe the panel_mipi_dsi.ko file.
2.) I created a device tree source based on this forum post and this device tree overlay. I have linked my dts file below as well. Riverdi also has a page on creating a device tree which I’ll link here, although I only used that to pull the init sequence (it includes the delays in the sequence, unlike the datasheet). I then compiled my dts→dtbo and pushed to the device with no errors.
3.) With those two items, I should see some activity on the screen, but I get nothing. Looking through the startup logs, I see the following when Weston starts up:
Starting Weston socket....
[OK] Listening on Weston Socket.
...
[8.031032] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.2 (ops 0xffffffc080c7b6a8)
[8.048374] imx-drm display-subsystem: bound imx-dpu-crtc.0 (ops 0xffffffc080c7b2b0)
[8.132123] imx-drm display-subsystem: bound imx-dpu-crtc.1 (ops 0xffffffc080c7b2b0)
[8.148096] imx8_media_dev: module is from the staging directory, the quality is unknown, you hav.
[8.152905] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1
From this, I found the following NXP forum post which claims that the minimum pixel clock available is 74.25MHz. My pixel clock is running at 51 MHz. I am not sure whether this is true in my case, as the Colibri claims that it can operate to much lower resolutions than I’m running at (see the datasheet page 50).
4.) I finally probed the pins to determine whether there is any obvious signal at the display. I totally expected garbage, as I don’t have good enough probes to really investigate the signal in finite detail. My probes claim to operate to 200 MHz, and so does my scope. I have had issues with these in the past, however. I have also included a scope picture with the probes on two sides of a differential pair. I can at least see that the edges I am seeing (whether they are just noise or something, I’m not certain) are in-phase and potentially mishapen. That would point to poor signal integrity. These are diffential signals and I would expect then to be out of phase, which I suppose points to noise. It definitely doesn’t look like MIPI, that’s for sure.
Anyways, I don’t know if anyone has answers to these questions, but I thought I’d ask. Any help is much appreciated. Can an interface board like the one posted below even be created for MIPI, or is it just too many connections to be feasible?
panel-mipi-dsi.c (22.5 KB)
