Colibri-iMX7D ENET2 RMII clock output

[qba]

Hello

What is the reason for 0x40000073, what do you want to achieve with 0x40000000

The reason was to set SION bit to get clock signal on output as in this thread:

I.mx7d fec2 internal reference clocking

I’m trying to bring up a board with a second Ethernet interface on a Colibri i.mx7D. We’re using RMII to connect a KSZ8041 PHY. In our design, the 50MHz reference clock is to be generated internal to the i.mx SoC and driven out the CCM_ENET2_REF_CLK path. Things are mostly working, but there’s no data going through the MAC. Some sleuthing suggests that the MAC is missing its reference clock, although that clock is enabled (see clk summary below) and is driving the PHY correctly. Here’s how we h…

No matter the value was 0x40000073 or 0x73 I had no clock output on SODIMM 106 pin. Only for a little time on boot with mentioned in first post patch.
We have designed 3 other devices with two active fec controllers with imx6ULL and without need to use external oscillators to drive PHY ics

Finally, after reading iMX7-colibri errata we decided to use external 50MHz oscillator like on Colibri board.

Here is the current device-tree fec2 node that works with ext 50MHz oscillator:

&fec2 {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&pinctrl_enet2>;
    pinctrl-1 = <&pinctrl_enet2_sleep>;
	
    clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
		<&clks IMX7D_ENET_AXI_ROOT_CLK>,
		<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
		<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <100000000>;
	
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_eth_vbus>;
	phy-reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <500>;
	phy-reset-post-delay = <100>;
	
	fsl,magic-packet;
	fsl,mii-exclusive;
	
	nvmem-cells = <&eth1_macaddr>;
    nvmem-cell-names = "mac-address";
    
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

	pinctrl_enet2: enet2grp {
		fsl,pins = <		
			MX7D_PAD_GPIO1_IO14__ENET2_MDIO	        0x1b0b0  /* SODIMM 188 */
			MX7D_PAD_GPIO1_IO15__ENET2_MDC          0x1b0b0  /* SODIMM 178 */
		
			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x73 /* SODIMM 122 */
			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0	0x73 /* SODIMM 114 */
			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1	    0x73 /* SODIMM 116 */
			MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER		0x73 /* SODIMM 124 */

			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL	0x73 /* SODIMM 133 */
			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0	0x73 /* SODIMM 127 */
			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1	0x73 /* SODIMM 130 */
			MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2   0x73 /* SODIMM 106 */
			
			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x73 /* SODIMM 112 - RST */
		>;
	};
	
    pinctrl_enet2_sleep: enet2sleepgrp {
        fsl,pins = <
            MX7D_PAD_GPIO1_IO14__GPIO1_IO14       0x0
            MX7D_PAD_GPIO1_IO15__GPIO1_IO15       0x0

            MX7D_PAD_EPDC_SDCE0__GPIO2_IO20       0x0
            MX7D_PAD_EPDC_SDCLK__GPIO2_IO16       0x0
            MX7D_PAD_EPDC_SDLE__GPIO2_IO17        0x0
            MX7D_PAD_EPDC_SDCE1__GPIO2_IO21       0x0

            MX7D_PAD_EPDC_GDRL__GPIO2_IO26        0x0
            MX7D_PAD_EPDC_SDCE2__GPIO2_IO22       0x0
            MX7D_PAD_EPDC_SDCE3__GPIO2_IO23       0x0
            MX7D_PAD_EPDC_BDR0__GPIO2_IO28        0x0
        >;
    };

I will mark this message as solution because fec2 finally works in our device