I’ve been cleaning up my device tree for my carrier board and I’ve come across a possible conflict.
I am using ALT3 for both can1 and can2 and have just noticed that both MX7D_PAD_SAI1_TX_BCLK and MX7D_PAD_SAI1_TX_DATA are used in pinctrl_gpmi_nand: gpmi-nand-grp.
The Toradex pinout designer lists this as possible, and it seem to run on my system. Are the gpmi_nand pins never used by the SOM ? (I really hope this is the answer).
NAND wouldn’t work if that conflict could take place. Why do you think your CAN2 has to do with PAD_SAI1_TX_BCLK/DATA pads? Which SODIMM contacts are you using for CAN’s? PAD names are specified in i.MX7 Ball Name column of 4.4.1 SODIMM 200 of Colibri iMX7 Datasheet.
The MX7D_PAD_SAI1_TX_BCLK and MX7D_PAD_SAI1_TX_DATA (and some other NAND related signals) are only available on Colibri iMX7D 1GB, not on the iMX7D 512MB or the iMX7S 256MB
Please check table 4.4.1 SODIMM 200 of Colibri iMX7 datasheet for details.
I am indeed using the iMX7D_1GB, so all is good. Thank you for the quick answer !
iMX7D_1GB doesn’t have a raw NAND, so all related pins are free for other uses.