Aquila AM69 Dev Board — using on-board FT4232H for JTAG debug (CCS / OpenOCD)?

Technical Support
1

Hi all,

I’m doing custom R5F firmware development on an Aquila AM69 SoM mounted on the V1.2B Aquila Development Board, and I’m trying to get JTAG debug access working. I’d like to know the intended workflow for using the on-board debugger.

Hardware setup:

  • Aquila AM69 SoM (J784S4 / AM69A) on Aquila Dev Board V1.2B

  • BSP 7.3.0

  • USB-C debug port connected to my laptop

What I see:

When I plug in the USB-C debug port, my host enumerates four FT4232H channels as standard USB serial ports (/dev/ttyUSB0..3 on Linux, COM ports on Windows). Looking at the dev board schematic, channel B’s ACBUS lines route to JTAG signals (TCK/TDI/TDO/TMS/TRST) and through a level shifter / mux (U59 TMUX1574) selectable between the FTDI and the external JTAG header J59 via jumper J58. Jumper J58 is currently installed/shorted (JTAG to FTDI).

So the hardware path appears to support on-board JTAG via the FT4232H, but in its default state all four channels enumerate as UART rather than one channel being available as MPSSE/JTAG.

What I’ve tried:

  1. CCS 12.4.0 with target config J784S4_TDA4VH and connection set to “Texas Instruments XDS110 USB Debug Probe”:
   An attempt to connect to the XDS110 failed.
   SC_ERR_XDS110_OPEN (-260 / 0xfffffefc)

I tried each of the XDS connection options (XDS100v2, XDS100v3, XDS110, XDS2xx variants) — all fail similarly. CCS doesn’t appear to recognize the FT4232H as an XDS-class probe.

  1. I’ve searched the forum and Toradex documentation but couldn’t find specific guidance on enabling JTAG via the on-board FTDI vs. requiring an external probe on J59.

Questions:

  1. Is the on-board FT4232H intended to be usable as a JTAG debugger for the SoC, or is it strictly a 4-channel UART bridge with the JTAG routing being a hardware option for Toradex internal use only?

  2. If on-board JTAG is a supported workflow, what setup is required? E.g., does the FT4232H EEPROM need to be reflashed (FT_PROG / ftdi_eeprom) to identify channel B as MPSSE? Are there pre-built EEPROM images Toradex can share?

  3. If the workflow is OpenOCD via libusb (rather than CCS) — does Toradex have an OpenOCD config file for the Aquila that documents the FTDI channel/pin layout (ftdi layout_init, layout_signal etc.)?

  4. If on-board JTAG is not supported, please confirm — I’ll switch to using the external J59 header with a SEGGER J-Link or similar probe. (J58 jumper position to “JTAG to Connector”.)

I’d much prefer using the on-board debugger if possible, since the schematic suggests the routing is already there. Any guidance from Toradex or other Aquila users who’ve done R5F-level debugging would be hugely appreciated.

Thanks!

Daniel

2

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

On-Board FT4232H JTAG Debug Support

Based on the Aquila Development Board documentation, the on-board FT4232H is indeed intended to provide JTAG debugging functionality for the SoC (1). The Aquila Development Board provides an on-board Universal USB Debugger (U15) based on the FT4232H chip with the following features (1):

  • 2x UART ports connected to the Aquila Module’s UART3 and UART4
  • JTAG Debugger/Programmer
  • 3x GPIO used for performing basic Development Board control features: Power ON/OFF, Reset and Recovery

FT4232H Pin Assignments for JTAG

The JTAG functionality is specifically mapped to the ACBUS pins of the FT4232H (1):

  • ACBUS0: JTAG_1_TCK (JTAG Test Clock)
  • ACBUS1: JTAG_1_TDI (JTAG Test Data Input)
  • ACBUS2: JTAG_1_TDO (JTAG Test Data Output)
  • ACBUS3: JTAG_1_TMS (JTAG Test Mode Select)
  • ACBUS4: JTAG1_TRST# (JTAG Test Mode Reset)

Hardware Configuration

The JTAG signals route through a multiplexer (TMUX1574) that allows selection between the on-board FTDI and external JTAG connector J59 (2). With jumper J58 installed (which you have), the JTAG signals are routed to the FTDI interface (2).

JTAG Interface Specifications

The JTAG interface operates at 1.8V levels (3) (4). The Aquila Family Specification notes that even though the nominal I/O voltage of the JTAG pins is 1.8V, it’s recommended to use the JTAG_1_VREF for the I/O voltage of the JTAG adapter, which offers more flexibility for Aquila modules with different JTAG I/O voltages (4).

External JTAG Connector Alternative

If you need to use an external JTAG debugger, the J59 connector provides a standard 10-pin 1.27mm Cortex Debug Connector interface (5). However, the documentation specifically warns that if an external JTAG debugger is used, jumper J58 should be removed, as simultaneous usage of the on-board and external JTAG debugger is not allowed and may damage the debugger or the development board (1).

Configuration Requirements

The fact that all four FT4232H channels enumerate as UART suggests that the EEPROM configuration may need to be modified to enable MPSSE mode on the JTAG channel. This would typically require reflashing the FT4232H EEPROM to properly identify one channel for JTAG/MPSSE functionality.

For specific OpenOCD configuration files or EEPROM programming details for the Aquila AM69, I’d recommend checking the Toradex Developer Center for the most current documentation, as the implementation details may vary between different Aquila variants.

Best regards, Toradex AI Assistant.

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Hi Alex,

Thank you for the detailed datasheet references — the J59 pinout and FT4232H channel B MPSSE pin mapping (TCK=26, TDI=27, TDO=28, TMS=29) are exactly what I needed to understand the hardware side.

However I’m still missing the software setup piece. What I know from your response:

  • Channel B of the FT4232H is wired for JTAG (MPSSE capable)
  • J58 installed routes JTAG signals to the FT4232H (confirmed)
  • J59 is the external connector alternative

What I still need to get this working:

  1. FT4232H EEPROM configuration — When the board enumerates, all four channels present as standard UART (RS232 mode). To use Channel B as JTAG/MPSSE, does the EEPROM need to be reflashed? If so, is there a Toradex-provided EEPROM image or .conf file for ftdi_eeprom? Or does Channel B switch to MPSSE automatically when an application (CCS/OpenOCD) claims it via libusb?

  2. CCS target configuration — Is there a .ccxml target configuration file for the Aquila AM69 / J784S4 that uses the on-board FT4232H as the debug probe? When I tried CCS 12.4 with “Texas Instruments XDS110 USB Debug Probe” it returned SC_ERR_XDS110_OPEN (-260) because the FT4232H doesn’t identify as an XDS device. Which connection type should I select in CCS for the on-board FTDI?

  3. OpenOCD configuration — Alternatively, is there an OpenOCD .cfg for this board? I’d need the ftdi layout_init and layout_signal values for Channel B, and a J784S4 target config. Does Toradex have these internally?

In short: the hardware is clearly capable, but I can’t find any documentation on how to actually connect a debugger to it. Is on-board JTAG via the FT4232H a supported and documented workflow for the Aquila AM69, or is the intended path to use an external probe on J59?

Thanks,
Daniel