Apalis TK1 PWM max frequency

We cannot set a frequency > 32KHz for PWM channels. The command is accepted but the output viewed at oscilloscope show a max of 32KHz.
After adding traces in pwm_tegra driver, it appears than the max clock rate is indeed 32768 (clk_get_rate(pwm->clk) function returns 32768).
We also found that clock source for pwm is ‘mux_pllp_pllc_clk32_clkm’. See in ‘linux/drivers/clk/tegra/clk-tegra-periph.c’
Is it really a limitation of this tegra soc?
Thank you,
Denis

No, Tegra K1 PWM is not limited by 32KHz. You can select another clock source for PWM by CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0 register. Please check chapter 36.0 PWM Controller of Tegra K1 Tech Ref Manual.

Which Linux branch you are referring to?

Thank you for quick answer. We are using 5.4.77 Linux branch.
Is it possible to change the PWM clock source by the DTB?

For your information:
tegra124 clock driver supports clock divider changes but does not supports clock source change. In our situation, default clock source for pwm is changed by u-boot to 32KHz clock. This source clock remains unchanged when linux boots and therefore the maximum clock rate is limited to 32KHz.
Changing the boot loader to select a pwm clock source to CLK_M (12MHz) resolve this problem.

Glad your problem is solved. Thanks for update.