Apalis iMX8 PCIE mode change to PCIE0 X2 lanes and PCIE1 X1 lane

Technical Support
, ,
1

Hi Support Team,

we want to make Apalis iMX8 (no wifi version) PCIE interface works with PCIE0 X2 and PCIE1 X1 mode instead of default PCIE0 X1, PCIE1 X1 and SATA mode.

HW configuration : Apalis iMX8QM 4GB IT with Ixora carrier
SW configuration: Ycoto Linux BSP minimal demo image V5.3

Tried with below device tree modification but no luck, the system boots hang with below attached boot log, not sure if it related to clock source issue or even need SCFW modification for some clock PLL configuration, kindly please help advise?

diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
index 4b6d0e846b32..7de7fc09a5b3 100644
--- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
@@ -309,7 +309,7 @@
 
 /* Apalis SATA1 */
 &sata {
-	status = "okay";
+	status = "disabled";
 };
 
 /* Apalis SPDIF1 */
diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
index bc35996ff744..22d8746d39c6 100644
--- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
@@ -1550,7 +1550,9 @@
 		      "pcie_phy", "phy_per", "pcie_per", "misc_per",
 		      "pcie_ext";
 
-	ext_osc = <1>;
+	num-lanes = <2>;
+        hsio-cfg = <PCIEAX2PCIEBX1>;
+        ext_osc = <1>;
 	fsl,max-link-speed = <1>;
 	reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie_switch>;
@@ -1559,23 +1561,30 @@
 /* On-module Wi-Fi */
 &pcieb {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>;
-	clocks = <&pcieb_lpcg 0>,
-		 <&pcieb_lpcg 1>,
-		 <&pcieb_lpcg 2>,
+	pinctrl-0 = <&pinctrl_pcieb>;
+        clocks = <&pcieb_lpcg 0>,
+                 <&pcieb_lpcg 1>,
+                 <&pcieb_lpcg 2>,
+                 <&phyx1_lpcg 0>,
+                 <&phyx1_lpcg 1>,
+                 <&phyx1_lpcg 2>,
+                 <&phyx2_crr0_lpcg 0>,
+                 <&phyx1_crr1_lpcg 0>,
+                 <&pciea_crr2_lpcg 0>,
+                 <&pcieb_crr3_lpcg 0>,
+                 <&misc_crr5_lpcg 0>,
+                 <&phyx2_lpcg 0>,
 		 <&phyx2_lpcg 1>,
-		 <&phyx2_lpcg 0>,
-		 <&phyx2_crr0_lpcg 0>,
-		 <&pcieb_crr3_lpcg 0>,
-		 <&pciea_crr2_lpcg 0>,
-		 <&misc_crr5_lpcg 0>,
-		 <&pcie_wifi_refclk_gate>;
-	clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
-		      "pcie_phy", "pcie_phy_pclk", "phy_per",
-		      "pcie_per", "pciex2_per", "misc_per",
-		      "pcie_ext";
+                 <&phyx1_lpcg 3>,
+                 <&pcie_sata_refclk_gate>;
+        clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
+                      "pcie_phy_pclk", "epcs_tx", "epcs_rx",
+                      "per_clk0", "phy_per", "pciex2_per",
+                      "pcie_per", "misc_per", "phy_pclk0",
+                      "phy_pclk1", "pcie_phy", "pcie_ext";
 	epdev_on-supply = <&reg_module_wifi>;
-	ext_osc = <1>;
+        hsio-cfg = <PCIEAX2PCIEBX1>;
+        ext_osc = <1>;
 	fsl,max-link-speed = <1>;
 	reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
 	status = "okay";

Thanks and Best Regards
Hai
boot_log.txt (25.0 KB)