Hi, we are trying to handle pin TAMPER, but we are not sure how to do it because what we did it doesn’t work . In order to do right things we must be sure about pins and how they were routed on SOM.
Pin 103 (TAMPER) is connected to ball E11 on IMX6Q?
pin 174 (VCCBACKUP) is connected to ball G11? is this pin the VDD_SNVS_IN?
which pin of the SOM corresponds to PMIC_ON_REQ? it would be useful for us in order to debug tamper.
Can you send us an image or tell us how to connect these pins? is there a specific connection?
i hope in a fast feedback. Please we need support urgently
The edge connector pin 103 is directly connected to the ball E11 of the SoC. There are no other components in between. Pin 174 is indirectly connected to the ball G11. The backup voltage goes into the PMIC, which features a 3.0V LDO that is permanently enabled. The 3.0V output of this LDO is connected to the ball G11 of the SoC.
The PMIC_ON_REQ signal is not available on the module edge connector. This signal directly connects ball D11 (SoC) and the pin 56 (PWRON) of the PMIC with a 100k pull-up resistor to the 3.0V RTC rail.
If I remember correctly, a special SoC fusing is required for using the tamper feature. Maybe this is why you are having issues handling the tamper pin.
Thanks but
By using “special SoC fusing is required” do you mean that we must put the CPU
in secure mode or we just need to write a special fuse to enable tamper detection?
We find nothing about this special setting within the CPU’s data sheet, are you
referring to a special application note? Or to which data sheet section?
I believe this only applies to the Vybrid and/or i.MX 6ULL. I could also not find any mention of any such “fuse” in any of them regular i.MX 6 manuals. Most of the tamper functionality is actually described in NXP’s security reference manual. I assume you already signed an NDA with NXP and got access to that secret document. I further assume you did notice the following sentence there:
2.2.1 Unsupported SNVS functions
The following functions are not supported by the SNVS due to lack of connectivity at the system level:
• Second external tamper input
• Voltage tamper input
• Temperature tamper input
• Two wire-mesh tamper input
Thanks, yes we signed nda and we have all documents but we continue to don’t understand well.
first of all , can we be sure that you did all you wrote in documents on the SOM?
Manuals specify almost nothing about Tamper. Too few information. we would need a design guide or clear image about handle tamper pin, because we did a hardware structure but it doesn’t work.
in our design tamper pin (103) is connected in serie with a switch in serie with pull up resistor on or structure 3v3/external battery.
or structure 3v3/external battery is also connected directly to pin 174 vcc_backup.
is this hardware correct? should we do something with software? if yes, what exactly?
Sorry, I really do not know. Until a couple of hours ago I was not even aware of our regular i.MX 6 based modules have such tamper functionality. NXP seems to have an app note about the topic albeit not for the i.MX 6 but rather a later SoC:
It looks like the i.MX 6 has similar tamper glitch filters and detectors configuration registers which you likely would need configuring for your exact use case. Anyway, all the information can be found in resp. security reference manual. Good luck!
