Apalis iMX6 LVDS Configuration

Hello,
I have an LVDS screen with a resolution of 1920x720.
I am set the following setting in U-boot:

setenv vidargs=video=mxcfb0:dev=ldb,1920x720M@60,if=RGB24 fbmem=32M

I follow this link and clone to compile the kernel.However, I am not sure which setting to make in imx6qdl-apalis.dtsi file on arch/arm/boot/dts path.

mxcfb1: fb@0 {
	compatible = "fsl,mxc_sdc_fb";
	disp_dev = "ldb";
	interface_pix_fmt = "RGB666";
	default_bpp = <16>;
	int_clk = <0>;
	late_init = <0>;
	status = "disabled";
};

    &ldb {
    	status = "okay";
    //	split-mode;
    //	dual-mode;
    
    	lvds-channel@0 {
    		reg = <0>;
    		fsl,data-mapping = "spwg"; /* "jeida"; */
    		fsl,data-width = <18>;
    		crtc = "ipu2-di1";
    		primary;
    		status = "okay";
    
    		display-timings {
    			native-mode = <&timing_xga>;
    			/* LDB-AM-800600LTNQW-A0H */
    			timing_svga: 800x600 {
    				clock-frequency = <55000000>;
    				hactive = <800>;
    				vactive = <600>;
    				hback-porch = <112>;
    				hfront-porch = <32>;
    				vback-porch = <3>;
    				vfront-porch = <17>;
    				hsync-len = <80>;
    				vsync-len = <4>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    			/* Standard XGA timing */
    			timing_xga: 1024x768 {
    				clock-frequency = <65000000>;
    				hactive = <1024>;
    				vactive = <768>;
    				hback-porch = <160>;
    				hfront-porch = <24>;
    				vback-porch = <29>;
    				vfront-porch = <3>;
    				hsync-len = <136>;
    				vsync-len = <6>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    			timing_wxga: 1280x800 {
    				clock-frequency = <68930000>;
    				hactive = <1280>;
    				vactive = <800>;
    				hback-porch = <64>;
    				hfront-porch = <64>;
    				vback-porch = <5>;
    				vfront-porch = <5>;
    				hsync-len = <40>;
    				vsync-len = <6>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    			/* LTTD1280800101-L4WH-CT1, note that it needs
    			   fsl,data-mapping = "spwg"; fsl,data-width = <24>; */
    			timing_wxga1: 1280x800-1 {
    				clock-frequency = <71100000>;
    				hactive = <1280>;
    				vactive = <800>;
    				hback-porch = <60>;
    				hfront-porch = <60>;
    				vback-porch = <7>;
    				vfront-porch = <7>;
    				hsync-len = <40>;
    				vsync-len = <9>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    			timing_fullhd: 1920x1080 {
    				clock-frequency = <138500000>;
    				hactive = <1920>;
    				vactive = <1080>;
    				hback-porch = <80>;
    				hfront-porch = <48>;
    				vback-porch = <23>;
    				vfront-porch = <3>;
    				hsync-len = <32>;
    				vsync-len = <5>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    		};
    	};
    
    	lvds-channel@1 {
    		reg = <1>;
    		fsl,data-mapping = "spwg";
    		fsl,data-width = <18>;
    		crtc = "ipu1-di0";
    		status = "okay";
    
    		display-timings {
    /*			native-mode = <&timing_svga_ch2>;*/
    			/* LDB-AM-800600LTNQW-A0H */
    			timing_svga_ch2: 800x600 {
    				clock-frequency = <55000000>;
    				hactive = <800>;
    				vactive = <600>;
    				hback-porch = <112>;
    				hfront-porch = <32>;
    				vback-porch = <3>;
    				vfront-porch = <17>;
    				hsync-len = <80>;
    				vsync-len = <4>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    				pixelclk-active = <0>;
    			};
    		};
    	};
    };

Can anyone help me.

Thanks

Hello

Since Bsp 2.6 or Kernel 3.14.52, we added back the possibility to set the display resolution from the kernel command line (see this site).

Best regards

Thanks for answer but I cant see any link.Can you renew?

hi, i corrected my post. Sorry, somehow the link got missing.

I read this article before. As I mentioned above, I enter the following command but the screen does not display.

setenv vidargs=video=mxcfb0:dev=ldb,1920x720M@60,if=RGB24 fbmem=32M

Where am I making mistakes?Do you have an idea?

hi

Could you provide the output of these commands:

  1. fbset
  2. cat /proc/cmdline

and the complete dmesg in a file? Thanks.

Hello again,

1- U-boot command:

setenv vidargs video=mxcfb0:dev=ldb,1920x720M@60,if=RGB24 fbmem=32M
saveenv

2- fbset output:

mode "1920x720-60"
    # D: 111.757 MHz, H: 44.774 kHz, V: 59.859 Hz
    geometry 1920 720 1920 720 16
    timings 8948 288 96 15 3 192 10
    vsync high
    rgba 5/11,6/5,5/0,0/0
endmode

3- cat /proc/cmdline output:

vmalloc=400M user_debug=30 ip=off root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait fec_mac= consoleblank=0 no_console_suspend=1 console=tty1 console=ttymxc0,115200n8 video=mxcfb0:dev=ldb,1920x720M@60,if=RGB24 fbmem=32M

4- dmesg output:
link text

Thanks.

hi

From Software side, it looks fine. Could you share the datasheet of the screen?
Thanks

The datasheet is here:
link text

Thanks for the Datasheet. You have to edit the display settings in the device tree as discussed here and set the parameters according to chapter 6 in the datasheet. You can overwrite the settings of timing_fullhd: 1920x1080 or create a new entry.

Hi

Your LCD has a single channel, four data pairs LVDS interface. The 24 bit color information is mapped in the VESA format (hopefully, the “Data mapping” table is ambiguous").

Note the i.MX 6’s LVDS display bridge single channel pixelclock must not exceed 85MHz.

So you would need to configure the color information in the device tree, additionally, to meet the pixelclock requirement you would also set the display timings in the device tree with the minimum blanking information your display allows and no longer specify it from the kernel command line.

E.g. changes similar to the following to the device tree:

--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -514,13 +514,28 @@
        lvds-channel@0 {
                reg = <0>;
                fsl,data-mapping = "spwg"; /* "jeida"; */
-               fsl,data-width = <18>;
+               fsl,data-width = <24>;
                crtc = "ipu2-di1";
                primary;
                status = "okay";
 
                display-timings {
-                       native-mode = <&timing_xga>;
+                       native-mode = <&timing_wide>;
+                       /* 12.3" WHD panel */
+                       timing_wide: 1920x720-1ch {
+                               clock-frequency = <85000000>;
+                               hactive = <1920>;
+                               vactive = <720>;
+                               hback-porch = <45>;
+                               hfront-porch = <44>;
+                               vback-porch = <2>;
+                               vfront-porch = <1>;
+                               hsync-len = <1>;
+                               vsync-len = <1>;
+                               hsync-active = <0>;
+                               vsync-active = <0>;
+                               pixelclk-active = <0>;
+                       };
                        /* LDB-AM-800600LTNQW-A0H */
                        timing_svga: 800x600 {
                                clock-frequency = <55000000>;

And vidargs along these lines:

setenv vidargs=video=mxcfb0:dev=ldb,if=RGB24 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

Max

hi Max,
Thank you for your answer. How can we obtain these values from interface timing section of the display datasheet? Should we get help from the display vendor?

                        /* 12.3" WHD panel */
                        timing_wide: 1920x720-1ch {
                                clock-frequency = <85000000>;
                                hactive = <1920>;
                                vactive = <720>;
                                hback-porch = <45>;
                                hfront-porch = <44>;
                                vback-porch = <2>;
                                vfront-porch = <1>;
                                hsync-len = <1>;
                                vsync-len = <1>;
                                hsync-active = <0>;
                                vsync-active = <0>;
                                pixelclk-active = <0>;
                        };

Thanks.

Hi

How about reading the datasheet and mixing in the 85MHz maximum pixelclock?

That is what I did to come up with my proposed settings above.

Your display only specifies DE (display enable) (aka. blanking) as the sync signal, e.g. it is not using HSync/VSync, so the blanking timing has to be distributed over the horizontal and vertical front-porch/sync-len/back-porch timings.

Max

Hi Max,
My configuration is as follows.
in imx6qdl-apalis.dtsi file:

         lvds-channel@0 {
                 reg = <0>;
                 fsl,data-mapping = "spwg"; /* "jeida"; */
                 fsl,data-width = <24>;
                 crtc = "ipu2-di1";
                 primary;
                 status = "okay";
  
                 display-timings {
                         native-mode = <&timing_wide>;

    /* 12.3" WHD panel */
                             timing_wide: 1920x720-1ch {
                                     clock-frequency = <85000000>;
                                     hactive = <1920>;
                                     vactive = <720>;
                                     hback-porch = <45>;
                                     hfront-porch = <44>;
                                     vback-porch = <2>;
                                     vfront-porch = <1>;
                                     hsync-len = <1>;
                                     vsync-len = <1>;
                                     hsync-active = <0>;
                                     vsync-active = <0>;
                                     pixelclk-active = <0>;
                             };

U-boot:

setenv vidargs video=mxcfb0:dev=ldb,if=RGB24 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

But still the screen is black.

I also see the following warning when debugging from a serial console.

apalis-imx6 login: [   12.650604] imx-ipuv3 2800000.ipu: IPU Warning - IPU_INT_STAT_10 = 0x00100000
[   12.650614] mxc_sdc_fb fb@0: 1920x720 h_sync,r,l: 1,44,45  v_sync,l,u: 1,1,2 pixclock=85005000 Hz
[   12.650623] imx-ipuv3 2800000.ipu: WARNING: adapt panel end blank lines

fbset output:

mode "1920x720-58"
    # D: 85.005 MHz, H: 42.291 kHz, V: 58.413 Hz
    geometry 1920 720 1920 720 16
    timings 11764 45 44 2 1 1 1
    rgba 5/11,6/5,5/0,0/0
endmode

cat /proc/cmdline output:

vmalloc=400M user_debug=30 ip=off root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait fec_mac=00:14:2d:4e:87:bf consoleblank=0 no_console_suspend=1 console=tty1 console=ttymxc0,115200n8 video=mxcfb0:dev=ldb,if=RGB24 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off fbmem=32M

Thanks.

Hi

imx-ipuv3 2800000.ipu: WARNING: adapt panel end blank lines

I guess this warning can be avoided by exchanging vback-porch and vfront-porch values to circumvent a i.MX6 limitation, however that will likely not change your display issue.

vback-porch = <1>;
vfront-porch = <2>;

Could you check and report:

  • is the backlight on?
  • is the wiring of the LVDS signals correct?
  • can you measure the LVDS clock signal?
  • can you post what exact signals you wired to what LCD pins?

Max

Hi Max,
As you said, it worked, but did not solve the display problem.

 vback-porch = <1>;
 vfront-porch = <2>;

I forwarded your questions to the electrical and electronics engineers. The answers are as below.

1-) Backlight is on.
2-)The LVDS signals wiring is correct.
3-) 70Mhz (LVDS Clock + , LVDS Clock -)
4-)
LCD signal name <=> IXORA signal name
LVDS Data3 +  <=>  LVDS1_A_TX3_P
LVDS Data3 -   <=>  LVDS_A_TX3_N
LVDS Data2 +   <=>  LVDS1_A_TX2_P
LVDS Data2 -   <=>  LVDS1_A_TX2_N
LVDS Data1+   <=>  LVDS1_A_TX1_P
LVDS Data1-   <=>  LVDS1_A_TX1_N
LVDS Data0 +   <=>  LVDS1_A_TX0_P
LVDS Data0 -   <=>  LVDS1_A_TX0_N
LVDS Clock +   <=>  LVDS1_A_CLK_P
LVDS Clock -   <=>   LVDS1_A_CLK_N 
GND <=> GND

Thanks.

hello
Thanks, but are these all the signals? Where are the power supply signals?

Hello jaski,
You can see below;

LCD signal name <=> IXORA signal name
Power Supply (3.3)   <=>   LVDS1_SEL_1
Power Supply (3.3)   <=>   LVDS1_3.3V_SW
Power Supply (3.3)   <=>   LVDS1_SEL_2
GND   <=>   GND

Thanks.

Hello
Thanks for the signals. It is difficult to reproduce the issue without having the same display on our side. Could you check with your display supplier, how the correct settings for hsync, vsync, … should be set?

Hello, Yes, I’ve asked them via email.The answer is as follows.

Our 12.3” product has no Back Porch and no Front Porch. The reason is that the Timing Controller in our panel is

not using H-sync and V-sync and  Back and Front Porch just describe the timing between data and H-Sync and V-Sync.

In case of AA123AD11 only DENA is used for synchronization (horizontally and vertically).

Below is a shortcut of datasheet of AA121AD11 page 26/27. There is no more timing information available and needed.

Two questions come to mind at this point.
1- Should we leave these values empty?

  • I tried this, but when I left it empty I got an error, but I’m not quite sure.

2- Should these values be 0?

  • The manufacturer says the product has no Porch. In this case If 0 has a meaning, would it be correct to write 0 to these values?

Thanks.