Apalis IMX6 EIM access


I try to make working EIM on Apalis IMX6Q and evalboard.
As EIM seems working on Colibri, i get the inspiration from colibri dtsi.
Attached you can find the whole dtsi i use :
[1]: https://share.toradex.com/oj2bfk7knfvpsly?direct

The main problem is that the EIm configuration written weems wrong :

root@apalis-imx6:~# devmem2 0x21b8000 w
/dev/mem opened.
Memory mapped at address 0x76f03000.
Read at address  0x021B8000 (0x76f03000): 0x00610089

As you can see it’s not the value configured in dtsi !

If you’ve an idea about the problem ?

(I use Yocto)

Thanks in advance


If the problem could help somebody…

In fact i forget to enable the EIM driver in kernel configuration. Now the dtsi parameters are well applied !

But i always have nothing on DATA[] pin at output.

devmem2 0x8000000 h 0x0000
devmem2 0x8000000 h 0xFFFF

gives nothing on EIM_DATA[] whereas EIM_CS0 level change.

if someone has an idea ?




Did you configure the driver into your kernel? (As our defconfig does not contain it).

root@apalis-imx6:~# zcat /proc/config.gz | grep WEIM                            
# CONFIG_IMX_WEIM is not set                                                    

Are there any issues reported in dmesg? e.g. as bei the following grep from a Colibri iMX6 were nothing went wrong:

root@colibri-imx6:~# dmesg | grep -i eim                                        
[    0.193965] imx-weim 21b8000.weim: Driver registered.


Hi Max,

Yes I’ve modified my defconfig to enable EIM :

root@apalis-imx6:~# zcat /proc/config.gz | grep WEIM
root@apalis-imx6:~# dmesg | grep -i eim
[    0.276755] imx-weim 21b8000.weim: Driver registered.

Remaining problem is : Writting on my CS0 peripheral doesn’t change DATA level on EIM bus.

Hi Max,

What i doesn’t understand is that when i wite:

devmem2 0x08000000 h 0x0000
→ address AD00 level is 0

devmem2 0x08000001 h 0x0000
→ address AD00 level is always 0

devmem2 0x08000002 h 0x0000
→ address AD00 level move to 1.

As you can see, it seems that there is a shift on address. (address bit 1 is EIM_AD00, address bit 2 is EIM_AD01…)

Can you explain me why ?

&weim {
	status = "okay";
	fsl,weim-cs-gpr = <&gpr>;
	/* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2, 32MB on CS3 */
	ranges = <0 0 0x08000000 0x02000000
	          1 0 0x0a000000 0x02000000
	          2 0 0x0c000000 0x02000000
	          3 0 0x0e000000 0x02000000>;
	/* SRAM on CS0 */
	sram@0,0 {
		compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
		reg = <0 0 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		bank-width = <2>;
		fsl,weim-cs-timing = <0x00020081 0x00000000 0x04000000
				0x00000000 0x04000040 0x00000000>;


One can configure the EIM addresses to be either byte addresses or ‘bus width’ word addresses.
Check the AUS bit in the configuration registers.

I’m unsure if you get sensible data back if your read spans a bus boundary, so reading 2 bytes from an uneven address would require two bus accesses.


Ok i’ve understand… According to PORT SIZE address are shifted.
documentation is not well explained on this point.
If i’ve a 32 bit data bus, i get 32 bit data on each request. So bit 0 and bit 1 are not used.
Perfect I’ve understand this point now…

But now i had to look why data level never change… Maybe i should look at other signal (WAIT, OE…)


The Colibri iMX6 dtb uses CS/OE/WE control signals, EIM_DATA[00:15] for the data, and EIM_AD00[00:15] for the address bus.

So I would start with CS/OE which should go down on read access and CS/WE which should go down on write access. Only then I would target the data/address bus signal.

I think the WAIT signal does not matter, or at least if not muxed it does not influence transactions.
Eventually you will have to use the reference manual and go through each field in the configuration registers and set it according to the bus device you are connecting.