Presently designing a custom carrier for an Apalis TK1, using the board design guide, and have two main questions regarding power shutdown handling. I assume the guide applies generically to the entire Apalis SOM family and would expect all requirements and behaviors discussed in the Power Management chapter to be uniformly applicable.
First Question: Fig 58 of the guide shows a shut-down sequence initiated by the SOM CPU, however, no minimum time is provided between POWER_ENABLE_MOCI falling edge and the module internal rails shutting down, making it impossible to know how long main VCC must remain valid after the falling edge. Are there any IOs on the MXM3 card edge that provide the on-module status of its power rails, ideally a signal that indicates “all clear” to switch the main power off?
Second Question: There is no information regarding loss of main power. Since figures 59 and 61 seem to imply that neither the RESET_MICO# nor WAKE1_MICO# affect the internal rails, There doesn’t appear to be an early power-fail detect input that prepares the module for imminent power loss. If RESET_MICO# is designated for this purpose, presumably setting the stage for safe power removal once the internal reset is asserted, I need to know the minimum time between the RESET_MICO# falling edge and the internal reset active. Is there a specification for the maximum time I need to hold up the main VCC following the RESET_MICO# assertion?