AM69 V1.1 USB_2_EN Line Low

Technical Support
, , , ,
1

Hi Support Team,

I’m working on a custom carrier board using the AM69 V1.1A (no BT no WIFI) SOM. We previously did development and testing on the Aquila development board rev 1.2 and the AM69 V1.0A SOM. On our custom carrier we have a regulator for one of our USB interfaces enabled by USB_2_EN, similar to the development board design. However, we see that this signal is low using the V1.1A SOM, and in the V1.0 SOM + dev board this line is high. We are using the version 7 BSP, yocto build. Is this expected? I see some errata regarding inversion on this line for the V1.0 SOM but not the v1.1 SOM. Our hardware is expecting an active high signal. Any help in debugging this would be appreciated. Thanks!

2

Hi, I’m the Toradex AI Assistant.

I might make mistakes or occasionally get you wrong. Our support team will step in if needed.

Based on the information in the Aquila AM69 documentation, this behavior is expected and related to the USB_2_EN signal changes between V1.0A and V1.1A.

Background on USB_2_EN Signal Changes

The USB_2_EN signal behavior changed between the Aquila AM69 V1.0A and V1.1A revisions. According to the errata documentation, the V1.0A had Errata #2 (HAR-11135) where the “USB_2_EN signal needs to be inverted (by default it’s active low output from the bridge)” (1).

The errata states that customers could not use the USB_2 interface with BSP 6-based software, but “the interface functions properly with operating systems based on BSP 7” (1). A software fix addressing this issue was implemented in BSP 7 (1).

V1.1A Changes

The V1.1A revision fixed this errata (1). However, this means the signal behavior has changed from what you experienced with V1.0A + development board combination.

Impact on Your Custom Carrier Board

Since your custom carrier board hardware is expecting an active high signal (based on your V1.0A + development board experience), but the V1.1A module now has the corrected signal behavior, you may need to:

  1. Verify your carrier board design - Check if your regulator enable circuit can work with the corrected USB_2_EN signal polarity from the V1.1A module
  2. Review the signal requirements - The V1.1A should provide the proper signal according to the Aquila family specification

Recommendation

Since you’re using BSP 7 with the V1.1A module, the USB_2_EN signal should be functioning according to the intended specification. If your custom carrier board was designed based on the V1.0A behavior (which had the errata), you may need to review your carrier board’s USB_2_EN handling circuit to ensure compatibility with the corrected V1.1A signal.

You can also use the tdx-info command to get detailed information about your current module and software versions. More information about this tool is available at: Getting Device Information with Tdx-Info | Toradex Developer Center

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.

3

@ToradexAI So, to be clear, the intended polarity on V1.1 is active low, rather than active high?

4

The documentation indicates that the V1.0A had an issue where the USB_2_EN signal was “active low output from the bridge” when it was designed to be active high (1). The errata states that “The USB_2_EN# pin is designed to be active low but is currently active high” (1).

This suggests that the intended specification for the USB_2_EN signal is active low (note the “#” symbol in “USB_2_EN#” which typically indicates an active-low signal). The V1.0A was incorrectly providing an active high signal, which was fixed in V1.1A (1).

So yes, to be clear: the intended polarity on V1.1A is active low, and your V1.1A module is now providing the correct signal behavior according to the Aquila family specification.

Since your custom carrier board was designed expecting the active high behavior from the V1.0A (which was incorrect), you’ll need to account for this signal polarity change in your carrier board design.

Best regards, Toradex AI Assistant.

Did you like my answer? :+1: :-1:

If I answered your question, please tick the “Solution” checkbox.

For follow-up questions to me, please use @ToradexAI in your post.