One customer would like to use SPI master on Colibri iMX8X with 60MHz clock. Testing with
spidev_test will meet following error:
root@colibri-imx8x:~# ./spidev_test -H -O -D /dev/spidev0.0 -s 60000000
spi mode: 3
bits per word: 8
max speed: 60000000 Hz (60000 KHz)
can't send spi message: Invalid argument
root@colibri-imx8x:~# [ 253.233858] fsl_lpspi 5a020000.lpspi: per-clk should be at least two times of transfer speed
[ 253.243170] spidev spi0.0: SPI transfer failed: -22
[ 253.248105] spi_master spi0: failed to transfer one message from queue
[ 253.254917] audit: type=1701 audit(1583819358.812:5): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=3999 comm="spidev_test" exe="/home/root/spidev_test" sig=6 res=1
Search on NXP community, I find this thread. It says one has to modify SCU to generate required clock for SPI. So does customer have to build customer SCFW according to our page?
You need to assign a different Parent Clock to the Spi Node.
Please have a look here.
Additionally to the setting of the spi parent clock you have to note the off-by-one-error in the driver for calculating the prescaler of the spi output clock.
I achieved a maximum frequency of 58,2 MHz by setting the max speed to e.g. 50 MHz.
thanks @jaski.tx and @Mowlwurf , with Oleksandr’s patch it can work with 60MHz.
Hi @jaski.tx , I measure 60MHz SPI clock output on SODIMM 88 with a oscilloscope but the clock wave is quite bad. [upload|MEcCo7BTxFmS96XY25IvX0MspXA=]
In device tree, SC_P_SPI2_SCK_ADMA_SPI2_SCK is already set to 0x06000040. According to iMX8QXP RM (188.8.131.52.100 SPI2_SCK (SPI2_SCK)), last bit PDRV is 0b which meaning output is configured in High Drive mode both in 1.8 V and 3.3 V applications.
When an external 10k resistor is added to pull SPI2_SCK to 3.3V, the wave does not get better.
However, the oscilloscope’s max bandwidth is 200MHz, 60MHz is close to this limitation for a sufficient sample. I don’t have more advanced oscilloscope here. Could you help to check if 60MHz output wave is ok? Thanks!
10MHz SPI clock is good.